ASIP design methodology

نویسندگان

  • Hervé Maréchal
  • Jack Kilby
چکیده

Hardware accelerators are commonly found in complex platforms. They assist in computing intensive tasks such as modem physical layer or multimedia codecs, which a central, general purpose processor could not perform quickly enough on its own. Such accelerators are typically handdesigned, hard-wired, and their very dedicated nature and instruction set usually doesn’t allow them to be programmed in a high-level programming language.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)

This paper introduces the concept and technology of Application-domain Specific Instruction-set Processor (ASIP). First, VLSI design trend over the decades is overviewed and processors are shown to be expected one of the main components in the System Level Design. Then, the advantage of ASIP over General Purpose Processor (GPP) and Application Specific Integrated Circuit (ASIC) is illustrated. ...

متن کامل

Verification Challenges in Configurable Processor Design with ASIP Meister

In this presentation, several verification problems in configurable processor design synthesis are illustrated. Our research group (PEAS Project) has been developing a novel design methodology of configurable processor, that includes higher level processor specification description, HDL description generation from the specification, Flexible Hardware Model (FHM) for resource management for HDL ...

متن کامل

The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models

We describe implementation of design automation tools that we have developed to automate system-level design using our ODYSSEY methodology, which advocates object-oriented (OO) modeling of the embedded system and ASIP-based implementation of it. Two flows are automated: one synthesizes an ASIP from a given C++ class library, and the other one compiles a given C++ application to run on the ASIP ...

متن کامل

Power efficient semi-automatic instruction encoding for application specific instruction set processors

A novel design methodology for the implementation of control units for application specific instruction set processors (ASIPS) is described. This methodology uses automatic instruction encoding and semi-automatic generation of the hardware instruction decoder to speed up the ASIP design. Significant power savings due to optimized instruction encoding are achieved. Results for ICORE (ISS-Core), ...

متن کامل

Power Reduction for Asips: a Case Study

Application specific instruction set processors (ASIPs) are an excellent architecture for mixed control/data-flow oriented tasks with medium to low data rate and high complexity. The main advantage of ASIPs is the higher flexibility due to programmability compared to dedicated hardware. A drawback of this design style is an increase in power consumption. The current case study focuses on an ASI...

متن کامل

Compiler-in-loop Architecture Exploration for Efficient Application Specific Embedded Processor Design

Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based on LISA, an industrial processor modeling language for efficient application-specific instruction set processor (ASIP) design. In order to circumvent the well-known trade-off between flexibility and code quality in re...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2006